1. Field of the Invention
The present invention relates to analog storage elements and arrays generally. More particularly, the present invention relates to an adaptable one-transistor analog storage element and an adaptable analog storage array comprising a plurality of one-transistor analog storage elements.
2. The Prior Art
Floating gate MOS transistors have been utilized in digital memory applications for over a decade. More recently, floating gate MOS technology has found use in analog applications. For example, in U.S. Pat. Nos. 4,890,259 and 4,989,179, analog floating gate devices are employed in an analog signal recording and playback system.
Many schemes have been proposed to use floating gate structures as weight storage for analog neural networks. Any such network requires a synaptic update mechanism which allows the weight to be changed depending on the combination of an input signal and an error signal. The desirable properties of such an update mechanism when implemented in an analog integrated circuit are small size, ability to work continuously (i.e., to use the signal while it is being updated), and freedom from high-voltage circuitry requirements within the synapse cell itself. The learning rate of such an update mechanism should not vary widely between circuits on the same chip.
In U.S. Pat. Nos. 4,935,702, and 5,068,622 to Mead et al., floating gate technology is used to control random offsets in analog amplifier elements. In U.S. Pat. No. 4,953,928 to Anderson et al., analog floating gates are employed in devices for performing the long term learning function. In U.S. Pat. No. 5,059,920 to Anderson et al., analog floating gates are employed in conjunction with devices containing electron injection and tunneling structures for performing an electrical learning function. In U.S. Pat. No. 5,083,044 to Mead et al., a synaptic element and array employ analog floating gate technology.
The prior art described in U.S. Pat. No. 5,059,920, and developed more recently by Mead et al. in co-pending application Ser. No. 07/805,324, filed Dec. 10, 1991, required rather complex structures occupying considerable area on the silicon surface. It would be desirable to further improve upon the devices disclosed in these references by providing similar functionality in structures utilizing less integrated circuit area per synapse.
Accordingly, it is an object of the present invention to provide a one-transistor synapse in a neural network.
It is a further object of the present invention to provide an array of synaptic elements, each containing only one transistor, the floating gate of any of which elements can be selectively either increased or decreased without appreciably disturbing the weights of other elements in the array.
A further object of the present invention is to provide a neural network including a plurality of synapses which occupies a smaller area than possible with prior art arrays.
This and other objects of the invention will be apparent to any person of ordinary skill in the art from the description of the invention contained herein.